02.10.2020
Suspension-Aware Earliest-Deadline-First Scheduling Analysis
Mario Günzel, Georg von der Brüggen, Jian-Jia Chen
18.08.2020
Correspondence Article: Counterexample for suspension-aware schedulability analysis of EDF scheduling
Mario Günzel, Jian-Jia Chen
18.06.2020
Model-based Optimization with Concept Drifts
Jakob Richter, Junjie Shi, Jian-Jia Chen, Jörg Rahnenführer and Michel Lang
11.02.2020
On Schedulability Analysis of EDF Scheduling by Considering Suspension as Blocking
Mario Günzel, Jian-Jia Chen
01.01.2020
Extendable Hardware-Based Main Memory Access Snooping for Non-volatile Memory Simulations and Analysis.
Junior Delrich Kamtchogom Namtchueng.
01.01.2020
Configurable FPGA-based Access Latency Emulation for Non-Volatile Main Memory
Dennis Morczinek
01.01.2020
NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-based FTL via NAND-SPIN
Wei-Chun Cheng, Shuo-Han Chen, Yuan-Hao Chang, Kuan-Hsun Chen, Jian-Jia Chen, Tseng-Yi Chen, Ming-Chang Yang and Wei-Kuan Shih
01.01.2020
Implementation of a Memory Access Trace Unit for a RISC-V SoC
Manuel Killinger
01.01.2020
A RISCV Emulation Board for Non-Volatile Memory
Ruoheng Ma
01.01.2020
Towards Explainable Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks.
Sebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler and Mikail Yayla