The illustration above shows a picture of the component. The component represents a multi-processor system with four processors and their corresponding cache memories. Each processor by default address the same memory block. Each line of the caches has its own state bits and therefore its own realization of a state-transition diagram. So the component displays four state-transition diagrams, one for each processor and its corresponding cache line.

The state transition diagrams include the four states "modified", "exclusive", "shared" and "invalid". With the two switches "read" and "write" at the left side of each diagram the user can control the application flow of the visualization.
To show how the MESI protocol works, the user should sequentially issue read and write requests from different diagrams and processors respectively. After a request, the diagrams display the resulting state transitions of the cache lines. The switches "read" and "write" issue a read and write request, respectively, of the processor. A read request for example is issued, if the switch "read" has the output value '1' (red). The output value '0' (grey) stands for a disabled request.