The schematic of the component "microprog" represents the hardware structure and at the same time it defines the appearance of the visualization. It shows the controller, the program counter "PC" with the write control gate "B", the memory unit "Mem", the instruction register "IR", the sign-extension unit "s.ex", the register file "Reg", the arithmetic and logical unit "ALU", the ALU control gate "Control", the ALU out register "T" and the gate "Concat" which has the task to build the jump address.
With the two switches "nreset" and "clock" the user can control the application flow of the visualization. The switch "nreset" enables the controller and the switch "clock" represents the manual clock cycle. We have not integrated a self-controlled clock signal because the clock cycles should be triggered by the user.

The thick light blue lines represent the control signals from the controller to the CPU. The thin light blue lines represent the signals between the datapath elements. If they are colored in light blue, they are not relevant in the actual cycle. The color "light blue" represent the logical value "undefined" in the Hades system.
The relevant signals in a cycle will be highlighted with different colors later during the visualization. This is important and quite different to the behaviour of a normal digital simulator system. A conventional simulator highlights all signal lines according to their values. Hence, for learning the basic concepts the conventional visualization is too complex and inconvenient.
 

The content of the memory unit, the current MIPS instructions, and the content of the register file are not determined by the component. The user can change them interactively during the visualization. The instructions in the memory unit can be entered either as assembler code or as 32bit strings. The register values of the register file have to be entered as 32bit strings. The default memory content and the default register file content are given in the file "mem.bin" and "reg.bin" respectively. These files are situated in the RaVi directory and will be loaded automatically during the start of the component.

The finite state machine realised in this component takes only those states into account which are necessary for the selected MIPS instructions of the component. This means that the implemented finite state machine specifies not a controller for the complete core MIPS instruction set.