Non-Volatile One Memory Architecture
Different forms of non-volatile memories (NVMs) have been introduced in the past decades. The recent development of NVMs has led to a promising future for building extra low-power computing systems when a NVM device is used as the media of both main memory and storage at the same time. However, most of the existing research results and system designs still consider NVM devices as additional memory or storage.
In this project, we consider the visionary embedded system architecture of using NVMs to replace DRAM, i.e., NVM is used as both main memory and storage (called one-memory architecture).
The project is coupled by two principle investigators (PI) from TU Dortmund and KIT in Germany and three PIs from Academia Sinica, National Taiwan University, and Chang Gung University in Taiwan. The applicant groups are domain experts in hardware-software codesign, embedded systems, non-volatile memories, power-efficient designs, and real-time systems.
Our project intends to provide the fundamental cornerstone of one-memory architectures that can be used to enable normally-off computing and improve battery-driven embedded systems. Our project aims to enable the effectiveness of one-memory architectures by performing design-space exploration in hardware and software designs, and by integrating analytical as well as optimized resource management in operating systems.
Activity Timeline
- 21.01.2022 -- Administrative Meeting @ Skype
- 14.01.2022 -- Administrative Meeting @ Skype
- 26.03.2021 -- Spring Workshop @ Zoom
- 20.02.2021 -- Tutorial @ VLSID 2021
- 01.02.2021 -- Tutorial @ DATE 2021
- 27.07.2020 -- Midterm Workshop @ Zoom
- 12.06.2020 -- Administrative Meeting @ Skype
- 17.02.2020 -- Project meeting @ Skype
- 03.12.2019 -- Project meeting @ KIT (Germany)
- 25.10.2019 -- Face-to-face meeting with NEC @ Heidelberg (Germany)
- 22.10.2019 -- Programming tutorial for NVM simulations @ TU Dortmund (Germany)
- 01.10.2019 -- Project meeting @ Dortmund (Germany)
- 16.05.2019 -- Project meeting @ KIT (Germany)
- 04.03.2019 -- Kickoff workshop @ Academia Sinica (Taiwan)
- 12.02.2019 -- Project meeting @ KIT (Germany)
Public Software
Published Software in general can be found in our Github Account
For various publications, we develop a modified NVM Simulator. In addition, we perform certain memory analysis on the simualtor output, espcially semantic memory analysis.
We also developed tools for evaluating the effect of errors stemming from unreliable memories on the inference accuracy of artificial neural networks. We provide a tool for error tolerance evaluation of binarized/quantized NNs. For applying error models on more general NNs, we created the tool BFITT which applies error models to PyTorch tensors.
Published Research Papers
2022
- Reliable Binarized Neural Networks on Unreliable Beyond von-Neumann Architecture
Mikail Yayla, Simon Thomann, Sebastian Buschjäger, Katharina Morik, Jian-Jia Chen and Hussam Amrouch
IEEE Transactions on Circuits and Systems I: Regular Papers
2022 - Efficient Realization of Decision Trees for Real-Time Inference
Kuan-Hsun Chen, ChiaHui Su, Christian Hakert, Sebastian Buschjäger, Chao-Lin Lee, Jenq-Kuen Lee, Katharina Morik, Jian-Jia Chen
Transactions on Embedded Computing Systems
2022 - This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator
Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai
27th Asia and South Pacific Design Automation Conference (ASP-DAC)
2022 - Memory-Efficient Training of Binarized Neural Networks on the Edge
Mikail Yayla and Jian-Jia Chen
Design Automation Conference (DAC'22, accepted for publication) - Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory
Christian Hakert, Kuan-Hsun Chen, Horst Schirmeier, Lars Bauer, Paul R. Genssler, Georg von der Brueggen, Hussam Amrouch, Joerg Henkel, Jian-Jia Chen
In ACM Transactions on Embedded Computing Systems, Volume 21, Issue 1, January 2022, Article No.: 5, pp 1–24 - FeFET-based Binarized Neural Networks Under Temperature-dependent Bit Errors
Mikail Yayla, Sebastian Bueschjager, Aniket Gupta, Jian-Jia Chen, Joerg Henkel, Katharina Morik, Kuan-Hsun Chen and Hussam Amrouch.
In IEEE Transactions on Computers (TC), accepted
2021
- Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization
Ming-Liang Wei, Mikail Yayla, SY. Ho, Chia-Lin Yang, Jian-Jia Chen, and Hussam Amrouch
In IEEE/ACM 40th International Conference on Computer-Aided Design (ICCAD'21) - OCTO+: Optimized Checkpointing of B+Trees for Non-Volatile Main Memory Wear-Leveling
Christian Hakert, Roland Kühn, Kuan-Hsun Chen, Jian-Jia Chen and Jens Teubner.
In 10th Non-Volatile Memory Systems and Applications Symposium, accepted - HEART: Hybrid memory and Energy-Aware Real-Time scheduling for multi-processor systems
Mario Guenzel, Christian Hakert, Kuan-Hsun Chen and Jian-Jia Chen.
In 21th International Conference on Embedded Software (EMSOFT)
ACM Transactions on Embedded Computing SystemsVolume 20, Issue 5s, October 2021, Article No.: 88, pp 1–23 - On the Reliability of FeFET On-Chip Memory
Paul R. Genssler, Victor M. van Santen, Joerg Henkel and Hussam Amrouch.
In IEEE Transactions on Computers (TC), accepted - BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory.
Christian Hakert, Asif-Ali Khan, Kuan-Hsun Chen, Fazal, Jeronimo Castrillon and Jian-Jia Chen.
In 58th ACM/IEEE Design Automation Conference (DAC) - Reptail: Cutting Storage Tail Latency with Inherent Redundancy
Yun-Chih Chen, Chun-Feng Wu, Yuan-Hao Chang, and Tei-Wei Kuo.
ACM/IEEE Design Automation Conference (DAC) - Heterogeneity-aware Multicore Synchronization for Intermittent Systems
Wei-Ming Chen, Tei-Wei Kuo, and Pi-Cheng Hsiu.
ACM Transactions on Embedded Computing Systems (TECS) - Space-efficient Graph Data Placement to Save Energy of ReRAM Crossbar
Ting-Hsuan Lo, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo, and Wei-Chen Wang.
ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Virtual Conference - How the common retention acceleration method of 3D NAND flash memory goes wrong?
Qiao Li, Min Ye, Tei-Wei Kuo, and Chun Jason Xue.
13th ACM Workshop on Hot Topics in Storage and File Systems (HotStorage '21), Best Paper Award - Pattern-Guided File Compression with User-Experience Enhancement for Log-Structured File System on Mobile Devices
Cheng Ji, Li-Pin Chang, Riwei Pan, Chao Wu, Congming Gao, Liang Shi, Tei-Wei Kuo, Chun Jason Xue.
USENIX Conference on File and Storage Technologies (FAST'21). Virtual Conference, February 23–25 - Read-ahead Efficiency on Mobile Devices: Observation, Characterization, and Optimization
Yu Liang, Riwei Pan, Yajuan Du, Chenchen Fu, Liang Shi, Tei-Wei Kuo, and Chun Jason Xue.
IEEE Transactions on Computers (TC), Volume: 70, Issue: 1, pp. 99-110 - Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses.
Ming-Ling Wei, Hussam Amrouch and Cheng-Lin Sung, Chia-Lin Yang, Khe-Chung Wang and Chin-Yuan Lu
In Proceedings of the IEEE 59th International Reliability Physics Symposium (IRPS). Virtual Conference - Margin-Marximization in Binarized Neural Networks for Optimizing Bit Error Tolerance.
Sebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler and Mikail Yayla.
In Design, Automation and Test in Europe Conference (DATE), Best Paper Award Candidate. Virtual Conference - Future Computing Platform Design: A Cross-Layer Design Approach.
Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang and Tei-Wei Kuo.
In Design, Automation and Test in Europe Conference (DATE), Special Session Paper. Virtual Conference - FeFET and NCFET for Future Neural Networks: Visions and Opportunities.
Mikail Yayla, Kuan-Hsun Chen, Georgios Zervakis, Joerg Henkel, Jian-Jia Chen and Hussam Amrouch.
In Design, Automation and Test in Europe Conference (DATE), Special Session Paper. Virtual Conference - Tutorial for Full System Simulations of Non-Volatile Main Memories.
Jian-Jia Chen and Christian Hakert.
In Design, Automation and Test in Europe Conference - [Demo] Tutorial for Full System Simulations of Non-Volatile Main Memories.
Christian Hakert and Jian-Jia Chen.
In Design, Automation and Test in Europe Conference
2020
- Enabling Failure-resilient Intermittent Systems Without Runtime Checkpointing.
Wei-Ming Chen, Tei-Wei Kuo, and Pi-Cheng Hsiu.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 39, Issue 12, pp. 4399-4412 - On Minimizing Analog Variation Errors to Resolve the Scalability Issue of ReRAM-Based Crossbar Accelerators.
Yao-Wen Kang, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo, and Shu-Yin Ho.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 39, Issue 11, pp. 3856-3867 - Pruning Deep Reinforcement Learning for Dual User Experience and Storage Lifetime Improvement on Mobile Devices.
Chao Wu, Yufei Cui, Cheng Ji, Tei-Wei Kuo, Chun Jason Xue.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 11, pp. 3993-4005 - When Storage Response Time Catches Up With Overall Context Switch Overhead, What Is Next?
Chun-Feng Wu, Yuan-Hao Chang, Ming-Chang Yang, and Tei-Wei Kuo.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 39, Issue 11, pp. 4266-4277 - Boosting User Experience via Foreground-Aware Cache Management in UFS Mobile Devices.
Chao Wu, Qiao Li, Cheng Ji, Tei-Wei Kuo, Chun Jason Xue.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 11, pp. 3263-3275 - Request Flow Coordination for Growing-Scale Solid-State Drives.
Ming-Chang Yang, Yuan-Hao Chang, Tei-Wei Kuo, and Chun-Feng Wu.
IEEE Transactions on Computers (TC), Volume 69, Issue 6, pp. 832-843 - Joint Management of CPU and NVDIMM for Breaking Down the Great Memory Wall.
Chun-Feng Wu, Yuan-Hao Chang, Ming-Chang Yang, and Tei-Wei Kuo.
IEEE Transactions on Computers (TC), Volume 69, Issue 5, pp. 722-733 - Shaving Retries with Sentinels for Fast Read over High-Density 3D Flash.
Qiao Li, Min Ye, Yufei Cui, Liang Shi, Xiaoqiang Li, Tei-Wei Kuo, Chun Jason Xue
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture (Micro). Athens, Greece - Valid Window: A New Metric to Measure the Reliability of NAND Flash Memory.
Min Ye, Qiao Li, Jianqiang Nie, Tei-Wei Kuo, and Chun Jason Xue.
Design Automation and Test Europe (DATE), pp.109-114, Virtual Conference - Overheating-Avoidance Remapping Scheme for Reliability Enhancement of 3D PCM Storage Systems.
Yu-Chen Lin, Tse-Yuan Wang, Che-Wei Tsao, Yuan-Hao Chang, Jian-Jia Chen, Xue Liu, Tei-Wei Kuo.
International Conference on Research in Adaptive and Convergent Systems (RACS) - Temperature Dependence and Temperature-Aware Sensing in Ferroelectric FET.
Aniket Gupta, Kai Ni, Om Prakash, X. Sharon Hu and Hussam Amrouch.
In Proceedings of the IEEE 58th International Reliability Physics Symposium (IRPS'20), Dallas, Texas - Impact of Extrinsic Variation Sources on the Device-to-Device Variation in Ferroelectric FET.
Kai Ni, Aniket Gupta, Om Prakash, Simon Thomann, X. Sharon Hu and Hussam Amrouch.
In Proceedings of the IEEE 58th International Reliability Physics Symposium (IRPS'20), Dallas, Texas - How to Cultivate a Green Decision Tree without Loss of Accuracy?.
Tseng-Yi Chen, Yuan-Hao Chang, Ming-Chang Yang and Huang-Wei Chen.
In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Virtual Conference - Software-Based Memory Analysis Environments for In-Memory Wear-Leveling.
Christian Hakert, Kuan-Hsun Chen, Mikail Yayla, Georg von der Brüggen, Sebastian Bloemeke and Jian-Jia Chen.
In 25th Asia and South Pacific Design Automation Conference ASP-DAC 2020, Invited Paper, Beijing, China - NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-based FTL via NAND-SPIN.
Wei-Chun Cheng, Shuo-Han Chen, Yuan-Hao Chang, Kuan-Hsun Chen, Jian-Jia Chen, Tseng-Yi Chen, Ming-Chang Yang and Wei-Kuan Shih.
In 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA), Virtual Conference - Split’n Trace NVM: Leveraging Library OSes for Semantic Memory Tracing.
Christian Hakert, Kuan-Hsun Chen, Simon Kuenzer, Sharan Santhanam, Shuo-Han Chen, Yuan-Hao Chang, Felipe Huici and Jian-Jia Chen.
In 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA), Virtual Conference - SoftWear: Software-Only In-Memory Wear-Leveling for Non-Volatile Main Memory.
Christian Hakert, Kuan-Hsun Chen, Paul R. Genssler, Georg Brüggen, Lars Bauer, Hussam Amrouch, Jian-Jia Chen and Jörg Henkel.
CoRR abs/2004.03244 - Towards Explainable Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks.
Sebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler and Mikail Yayla.
CoRR abs/2002.00909
2019
- Stack Usage Analysis for Efficient Wear Leveling in Non-Volatile Main Memory Systems.
Christian Hakert, Mikail Yayla, Kuan-Hsun Chen, Georg von der Brüggen, Jian-Jia Chen, Sebastian Buschjäger, Katharina Morik, Paul R. Genssler, Lars Bauer, Hussam Amrouch and Jörg Henkel.
In 1st ACM/IEEE Workshop on Machine Learning for CAD (MLCAD)
Alberta, Canada, 2019 - The Best of Both Worlds: On Exploiting Bit-Alterable NAND Flash for Lifetime and Read Performance Optimization.
Shuo-Han Chen, Ming-Chang Yang and Yuan-Hao Chang.
In Proceedings of the 56th Annual Design Automation Conference (DAC)
2019 - Replanting Your Forest: NVM-friendly Bagging Strategy for Random Forest.
Yu Ting Ho, Chun-Feng Wu, Ming-Chang Yang, Yseng-Yi Chen and Yuan-Hao Chang.
In Non-Volatile Memory Systems and Applications Symposium (NVMSA)
2019 - Adaptive Memory and Storage Fusion on Non-Volatile One-Memory System.
Chi-Hsing Chang and Che-Wei Chang.
In Non-Volatile Memory Systems and Applications Symposium (NVMSA)
2019
Student Theses
2020
- A RISCV Emulation Board for Non-Volatile Memory.
Ruoheng Ma.
Bachelor Thesis, 2020 - Implementation of a Memory Access Trace Unit for a RISC-V SoC.
Manuel Killinger.
Bachelor Thesis, 2020 - Configurable FPGA-based Access Latency Emulation for Non-Volatile Main Memory.
Dennis Morczinek.
Bachelor Thesis, 2020 - Extendable Hardware-Based Main Memory Access Snooping for Non-volatile Memory Simulations and Analysis.
Junior Delrich Kamtchogom Namtchueng.
Bachelor Thesis, 2020
2019
- Memory Access Analysis and Endurance Leveling Approaches for Non-volatile Working Memory Systems.
Christian Hakert.
Master's Thesis, 2019 - Analysis and Optimization of Trace-Based Simulator for Non-Volatile Main Memory.
Sebastian Blömeke.
Bachelor Thesis, 2019