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NVM-OMA

Non-Volatile One Memory Architecture

Different forms of non-volatile memories (NVMs) have been introduced in the past decades. The recent development of NVMs has led to a promising fu­ture for building extra low-power computing systems when a NVM device is used as the media of both main memory and storage at the same time. However, most of the existing re­search results and system designs still consider NVM devices as additional memory or storage.

In this proj­ect, we consider the visionary embedded system architecture of using NVMs to replace DRAM, i.e., NVM is used as both main memory and storage (called one-memory architecture).

The proj­ect is coupled by two principle investigators (PI) from TU Dort­mund and KIT in Germany and three PIs from Academia Sinica, National Taiwan Uni­ver­sity, and Chang Gung Uni­ver­sity in Taiwan. The applicant groups are domain experts in hardware-software codesign, embedded systems, non-volatile memories, power-efficient designs, and real-time systems.

Our proj­ect intends to provide the fundamental cornerstone of one-memory architectures that can be used to enable normally-off computing and improve battery-driven embedded systems. Our proj­ect aims to enable the effectiveness of one-memory architectures by performing de­sign-space exploration in hardware and software designs, and by integrating analytical as well as optimized resource management in operating systems.

Activity Timeline

  • 26.03.2021 -- Spring Work­shop @ Zoom
  • 20.02.2021 -- Tutorial @ VLSID 2021 
  • 01.02.2021 -- Tutorial @ DATE 2021
  • 27.07.2020 -- Midterm Work­shop @ Zoom
  • 12.06.2020 -- Administrative Meeting @ Skype
  • 17.02.2020 -- Project meeting @ Skype
  • 03.12.2019 -- Project meeting @ KIT (Germany)
  • 25.10.2019 -- Face-to-face meeting with NEC @ Heidelberg (Germany)
  • 22.10.2019 -- Programming tutorial for NVM simulations @ TU Dort­mund (Germany)
  • 01.10.2019 -- Project meeting @ Dort­mund (Germany)
  • 16.05.2019 -- Project meeting @ KIT (Germany)
  • 04.03.2019 -- Kickoff workshop @ Academia Sinica (Taiwan)
  • 12.02.2019 -- Project meeting @ KIT (Germany)

Links: DFG, MOST

 

 

Published Research Papers

2021

  • Soft­ware-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory
    Christian Hakert, Kuan-Hsun Chen, Horst Schirmeier, Lars Bauer, Paul R. Genssler, Georg von der Brueggen, Hussam Amrouch, Joerg Henkel, Jian-Jia Chen
    In ACM Transactions on Embedded Computing Systems, accepted
  • FeFET-based Binarized Neural Networks Under Temperature-dependent Bit Errors
    Mikail Yayla, Se­bas­ti­an Bueschjager,  Aniket Gupta,  Jian-Jia Chen, Joerg Henkel, Katharina Morik, Kuan-Hsun Chen and Hussam Amrouch.
    In IEEE Transactions on Computers (TC),  accepted
  • Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization
    Ming-Liang Wei, Mikail Yayla, SY. Ho, Chia-Lin Yang, Jian-Jia Chen, and Hussam Amrouch
    In IEEE/ACM 40th International Conference on Computer-Aided Design (ICCAD'21)
  • OCTO+: Optimized Checkpointing of B+Trees for Non-Volatile Main Memory Wear-Leveling
    Christian Hakert, Roland Kühn, Kuan-Hsun Chen, Jian-Jia Chen and Jens Teubner.
    In 10th Non-Volatile Memory Systems and Applications Symposium,  accepted
  • HEART: Hybrid memory and Energy-Aware Real-Time scheduling for multi-processor systems
    Mario Guenzel, Christian Hakert, Kuan-Hsun Chen and Jian-Jia Chen.
    In 21th International Conference on Embedded Soft­ware (EMSOFT),  accepted
  • On the Reliability of FeFET On-Chip Memory
    Paul R. Genssler, Victor M. van Santen, Joerg Henkel and Hussam Amrouch.
    In IEEE Transactions on Computers (TC),  accepted
  • BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory.
    Christian Hakert, Asif-Ali Khan, Kuan-Hsun Chen, Fazal, Jeronimo Castrillon and Jian-Jia Chen. 
    In 58th ACM/IEEE Design Automation Conference (DAC), accepted
  • Reptail: Cutting Storage Tail Latency with Inherent Redundancy
    Yun-Chih Chen, Chun-Feng Wu, Yuan-Hao Chang, and  Tei-Wei Kuo.
    ACM/IEEE Design Automation Conference (DAC), accepted
  • Heterogeneity-aware Multicore Synchronization for Intermittent Systems
    Wei-Ming Chen, Tei-Wei Kuo, and Pi-Cheng Hsiu.
    ACM Transactions on Embedded Computing Systems (TECS), accepted
  • Space-efficient Graph Data Placement to Save Energy of ReRAM Crossbar
    Ting-Hsuan Lo, Chun-Feng Wu, Yuan-Hao Chang,  Tei-Wei Kuo, and Wei-Chen Wang.
    ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Virtual Conference
  • How the common retention acceleration method of 3D NAND flash memory goes wrong?
    Qiao Li, Min Ye, Tei-Wei Kuo, and Chun Jason Xue.
    13th ACM Work­shop on Hot Topics in Storage and File Systems (HotStorage '21), Best Paper Award
  • Pattern-Guided File Compression with User-Experience Enhancement for Log-Structured File System on Mobile Devices
    Cheng Ji, Li-Pin Chang, Riwei Pan, Chao Wu, Congming Gao, Liang Shi, Tei-Wei Kuo, Chun Jason Xue.
    USENIX Conference on File and Storage Technologies (FAST'21). Virtual Conference, February 23–25
  • Read-ahead Efficiency on Mobile Devices: Observation, Characterization, and Optimization
    Yu Liang, Riwei Pan, Yajuan Du, Chenchen Fu, Liang Shi, Tei-Wei Kuo, and Chun Jason Xue.
    IEEE Transactions on Computers (TC), Volume: 70, Issue: 1, pp. 99-110
  • Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses.
    Ming-Ling Wei, Hussam Amrouch and Cheng-Lin Sung, Chia-Lin Yang, Khe-Chung Wang and Chin-Yuan Lu
    In Proceedings of the IEEE 59th International Reliability Physics Symposium (IRPS). Virtual Conference
  • Margin-Marximization in Binarized Neural Networks for Optimizing Bit Error Tolerance.
    Se­bas­ti­an Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler and Mikail Yayla.
    In Design, Automation and Test in Europe Conference (DATE), Best Paper Award Candidate. Virtual Conference
  • Future Computing Platform Design: A Cross-Layer Design Approach.
    Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang and Tei-Wei Kuo.
    In Design, Automation and Test in Europe Conference (DATE), Special Session Paper. Virtual Conference
  • FeFET and NCFET for Future Neural Networks: Visions and Opportunities.
    Mikail Yayla, Kuan-Hsun Chen, Georgios Zervakis, Joerg Henkel, Jian-Jia Chen and Hussam Amrouch.
    In Design, Automation and Test in Europe Conference (DATE), Special Session Paper. Virtual Conference
  • Tutorial for Full System Simulations of Non-Volatile Main Memories.
    Jian-Jia Chen and Christian Hakert.
    In Design, Automation and Test in Europe Conference
  • [Demo] Tutorial for Full System Simulations of Non-Volatile Main Memories.
    Christian Hakert and Jian-Jia Chen.
    In Design, Automation and Test in Europe Conference

2020

  • Enabling Failure-resilient Intermittent Systems Without Runtime Checkpointing.
    Wei-Ming Chen, Tei-Wei Kuo, and Pi-Cheng Hsiu.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 39, Issue 12, pp. 4399-4412
  • On Minimizing Analog Variation Errors to Resolve the Scalability Issue of ReRAM-Based Crossbar Accelerators.
    Yao-Wen Kang, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo, and Shu-Yin Ho.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 39, Issue 11, pp. 3856-3867
  • Pruning Deep Reinforcement Learn­ing for Dual User Experience and Storage Lifetime Improvement on Mobile Devices.
    Chao Wu, Yufei Cui, Cheng Ji, Tei-Wei Kuo, Chun Jason Xue.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 11, pp. 3993-4005
  • When Storage Response Time Catches Up With Overall Context Switch Overhead, What Is Next?
    Chun-Feng Wu, Yuan-Hao Chang, Ming-Chang Yang, and Tei-Wei Kuo.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 39, Issue 11, pp. 4266-4277
  • Boosting User Experience via Foreground-Aware Cache Management in UFS Mobile Devices.
    Chao Wu, Qiao Li, Cheng Ji, Tei-Wei Kuo, Chun Jason Xue.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 11, pp. 3263-3275
  • Request Flow Coordination for Growing-Scale Solid-State Drives.
    Ming-Chang Yang, Yuan-Hao Chang, Tei-Wei Kuo, and Chun-Feng Wu.
    IEEE Transactions on Computers (TC), Volume 69, Issue 6, pp. 832-843
  • Joint Management of CPU and NVDIMM for Breaking Down the Great Memory Wall.
    Chun-Feng Wu, Yuan-Hao Chang, Ming-Chang Yang, and Tei-Wei Kuo.
    IEEE Transactions on Computers (TC), Volume 69, Issue 5, pp. 722-733
  • Shaving Retries with Sentinels for Fast Read over High-Density 3D Flash.
    Qiao Li, Min Ye, Yufei Cui, Liang Shi, Xiaoqiang Li, Tei-Wei Kuo, Chun Jason Xue
    Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture (Micro). Athens, Greece
  • Valid Window: A New Metric to Measure the Reliability of NAND Flash Memory.
    Min Ye, Qiao Li, Jianqiang Nie, Tei-Wei Kuo, and Chun Jason Xue.
    Design Automation and Test Europe (DATE), pp.109-114, Virtual Conference
  • Overheating-Avoidance Remapping Scheme for Reliability Enhancement of 3D PCM Storage Systems.
    Yu-Chen Lin, Tse-Yuan Wang, Che-Wei Tsao, Yuan-Hao Chang, Jian-Jia Chen, Xue Liu, Tei-Wei Kuo.
    International Conference on Research in Adaptive and Convergent Systems (RACS)
  • Temperature Dependence and Temperature-Aware Sensing in Ferroelectric FET.
    Aniket Gupta, Kai Ni, Om Prakash, X. Sharon Hu and Hussam Amrouch.
    In Proceedings of the IEEE 58th International Reliability Physics Symposium (IRPS'20), Dallas, Texas
  • Impact of Extrinsic Variation Sources on the Device-to-Device Variation in Ferroelectric FET.
    Kai Ni, Aniket Gupta, Om Prakash, Simon Thomann, X. Sharon Hu and Hussam Amrouch.
    In Proceedings of the IEEE 58th International Reliability Physics Symposium (IRPS'20), Dallas, Texas
  • How to Cultivate a Green Decision Tree without Loss of Accuracy?.
    Tseng-Yi Chen, Yuan-Hao Chang, Ming-Chang Yang and Huang-Wei Chen.
    In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Virtual Conference
  • Soft­ware-Based Memory Analysis Environments for In-Memory Wear-Leveling.
    Christian Hakert, Kuan-Hsun Chen, Mikail Yayla, Georg von der Brüggen, Se­bas­ti­an Bloemeke and Jian-Jia Chen.
    In 25th Asia and South Pacific Design Automation Conference ASP-DAC 2020, Invited Paper, Beijing, China
  • NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-based FTL via NAND-SPIN.
    Wei-Chun Cheng, Shuo-Han Chen, Yuan-Hao Chang, Kuan-Hsun Chen, Jian-Jia Chen, Tseng-Yi Chen, Ming-Chang Yang and Wei-Kuan Shih.
    In 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA), Virtual Conference
  • Split’n Trace NVM: Leveraging Library OSes for Semantic Memory Tracing.
    Christian Hakert, Kuan-Hsun Chen, Simon Kuenzer, Sharan Santhanam, Shuo-Han Chen, Yuan-Hao Chang, Felipe Huici and Jian-Jia Chen.
    In 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA), Virtual Conference
  • SoftWear: Soft­ware-Only In-Memory Wear-Leveling for Non-Volatile Main Memory.
    Christian Hakert, Kuan-Hsun Chen, Paul R. Genssler, Georg Brüggen, Lars Bauer, Hussam Amrouch, Jian-Jia Chen and Jörg Henkel.
    CoRR abs/2004.03244
  • Towards Explainable Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks.
    Se­bas­ti­an Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler and Mikail Yayla.
    CoRR abs/2002.00909

2019

  • Stack Usage Analysis for Efficient Wear Leveling in Non-Volatile Main Memory Systems.
    Christian Hakert, Mikail Yayla, Kuan-Hsun Chen, Georg von der Brüggen, Jian-Jia Chen, Se­bas­ti­an Buschjäger, Katharina Morik, Paul R. Genssler, Lars Bauer, Hussam Amrouch and Jörg Henkel.
    In 1st ACM/IEEE Work­shop on Machine Learn­ing for CAD (MLCAD)
    Alberta, Canada, 2019
  • The Best of Both Worlds: On Exploiting Bit-Alterable NAND Flash for Lifetime and Read Per­for­mance Optimization.
    Shuo-Han Chen, Ming-Chang Yang and Yuan-Hao Chang.
    In Proceedings of the 56th Annual Design Automation Conference (DAC)
    2019
  • Replanting Your Forest: NVM-friendly Bagging Strategy for Random Forest.
    Yu Ting Ho, Chun-Feng Wu, Ming-Chang Yang, Yseng-Yi Chen and Yuan-Hao Chang.
    In Non-Volatile Memory Systems and Applications Symposium (NVMSA)
    2019
  • Adaptive Memory and Storage Fusion on Non-Volatile One-Memory System.
    Chi-Hsing Chang and Che-Wei Chang.
    In Non-Volatile Memory Systems and Applications Symposium (NVMSA)
    2019

Location & approach

The campus of TU Dort­mund Uni­ver­sity is located close to interstate junction Dort­mund West, where the Sauerlandlinie A 45 (Frankfurt-Dort­mund) crosses the Ruhrschnellweg B 1 / A 40. The best interstate exit to take from A 45 is "Dort­mund-Eichlinghofen" (closer to Cam­pus Süd), and from B 1 / A 40 "Dort­mund-Dorstfeld" (closer to Cam­pus Nord). Signs for the uni­ver­si­ty are located at both exits. Also, there is a new exit before you pass over the B 1-bridge leading into Dort­mund.

To get from Cam­pus Nord to Cam­pus Süd by car, there is the connection via Vo­gel­pothsweg/Baroper Straße. We recommend you leave your car on one of the parking lots at Cam­pus Nord and use the H-Bahn (suspended monorail system), which conveniently connects the two campuses.

TU Dort­mund Uni­ver­sity has its own train station ("Dort­mund Uni­ver­si­tät"). From there, suburban trains (S-Bahn) leave for Dort­mund main station ("Dort­mund Hauptbahnhof") and Düsseldorf main station via the "Düsseldorf Airport Train Station" (take S-Bahn number 1, which leaves every 20 or 30 minutes). The uni­ver­si­ty is easily reached from Bochum, Essen, Mülheim an der Ruhr and Duis­burg.

You can also take the bus or subway train from Dort­mund city to the uni­ver­si­ty: From Dort­mund main station, you can take any train bound for the Station "Stadtgarten", usually lines U41, U45, U 47 and U49. At "Stadtgarten" you switch trains and get on line U42 towards "Hombruch". Look out for the Station "An der Palmweide". From the bus stop just across the road, busses bound for TU Dort­mund Uni­ver­sity leave every ten minutes (445, 447 and 462). Another option is to take the subway routes U41, U45, U47 and U49 from Dort­mund main station to the stop "Dort­mund Kampstraße". From there, take U43 or U44 to the stop "Dort­mund Wittener Straße". Switch to bus line 447 and get off at "Dort­mund Uni­ver­si­tät S".

The AirportExpress is a fast and convenient means of transport from Dort­mund Airport (DTM) to Dort­mund Central Station, taking you there in little more than 20 minutes. From Dort­mund Central Station, you can continue to the uni­ver­si­ty campus by interurban railway (S-Bahn). A larger range of in­ter­na­tio­nal flight connections is offered at Düsseldorf Airport (DUS), which is about 60 kilometres away and can be directly reached by S-Bahn from the uni­ver­si­ty station.

The H-Bahn is one of the hallmarks of TU Dort­mund Uni­ver­sity. There are two stations on Cam­pus Nord. One ("Dort­mund Uni­ver­si­tät S") is directly located at the suburban train stop, which connects the uni­ver­si­ty directly with the city of Dort­mund and the rest of the Ruhr Area. Also from this station, there are connections to the "Technologiepark" and (via Cam­pus Süd) Eichlinghofen. The other station is located at the dining hall at Cam­pus Nord and offers a direct connection to Cam­pus Süd every five minutes.

The facilities of TU Dort­mund Uni­ver­sity are spread over two campuses, the larger Cam­pus North and the smaller Cam­pus South. Additionally, some areas of the uni­ver­si­ty are located in the adjacent "Technologiepark".

Site Map of TU Dort­mund Uni­ver­sity (Second Page in English).